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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4738V LSI IEC/IEEE bus interface
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
IEC/IEEE bus interface
DESCRIPTION The HEF4738V is an implementation of the IEC-bus as described in IEC report 66 CO 22 (interface system for programmable measuring apparatus) as well as in IEEE standard 488-1975 (standard digital interface for programmable instrumentation). Together with bus-drivers, level converters and multiplexers it is suitable for connecting electronic programmable and non-programmable equipment to an IEC/IEEE interface bus. All inputs have standard HE4000B family levels. In the circuit the following standard interface functions are incorporated:
HEF4738V LSI
* Complete source handshake (subset SH1) * Complete acceptor handshake (subset AH1) * Basic talker with serial poll and talk-only mode (when It = LOW, subset T1; It = HIGH, subset T5) * Basic listener with listen-only mode (when It = LOW, subset L1; It = HIGH, subset L3) * Complete service request (subset SR1) * Complete remote local (subset RL1) * Remote parallel poll configuration (subset PP1) * Complete device clear (subset DC1) * Complete device trigger (subset DT1) * Some controller facilities
Fig.1 Basic IEC/IEEE bus interface using the HEF4738V.
SUPPLY VOLTAGE RATING -0,5 to 18 RECOMMENDED OPERATING 4,5 to 12,5 V
FAMILY DATA, IDD LIMITS category LSI See Family Specifications
January 1995
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Philips Semiconductors
Product specification
IEC/IEEE bus interface
GENERAL DESCRIPTION The inputs IRFD, IDAC, IDAV, IIFC, IREN, IATN, IIDY and IDIO1 to IDIO7 must be connected via an inverting TTL to LOCMOS level converter to the respective bus lines: NRFD, NDAC, DAV, IFC, REN, ATN, IDY and DIO1 to DIO7. The outputs ORFD, ODAC, ODAV and OSRQ can drive one standard TTL load and are suitable for driving NRFD, NDAC, DAV and SRQ via an inverting bus-driver circuit. The parallel poll outputs OP1, OP2, OP3 and OPP can also drive one standard TTL load. Outputs OP1, OP2 and OP3 are connected to flip-flops, which store the attendant bits P1, P2 and P3 of the last PPE message. OP1, OP2 and OP3 have to be decoded externally and multiplexed to the DIO-lines when OPP is LOW. All other output stages are standard HE4000B family. Most of the functions in the IEC/IEEE interface IC are realized with synchronous sequential logic, which is driven from the clock input CP. HIGH to LOW transitions are used to synchronize input signals and LOW to HIGH transitions trigger the internal flip-flops. In order to meet the IEC/IEEE timing specifications, the maximum clock frequency is 2 MHz. The maximum data transfer is then 200 kbytes/second. Input Irdy (not ready for next message) and output Odvd (data valid device) are intended for a two-wire handshake procedure between the acceptor function in the IC and the data input of the device (instrument to be connected to the interface system). The procedure is made so, that if the device reacts fast enough, the handshake procedure can be omitted by interconnecting Odvd and Irdy. The conditions to be fulfilled by the device are: * The device must be able to accept a data byte within one clock period after dvd goes HIGH under all conditions. * The device must be ready to process a data byte within two clock periods plus the minimum settling time of the talker devices under all conditions. Input Inba (not new byte available) and output Odcd (don't change data) are intended for a two-wire handshake procedure with the source function in the IC and the data output of the device (instrument). The procedure is so made that if the device reacts fast enough the handshake procedure can be omitted by interconnecting Odcd and Inba. The conditions to be fulfilled by the device are: * The device must be able to set a new data byte on the bus within one clock period after dcd goes LOW under all conditions. * The device must be able to have the next data byte available within seven clock periods under all conditions.
HEF4738V LSI
Input Isr and output Ored should be connected to an external parallel-in/serial-out (when Ored is HIGH parallel-in, when LOW serial-out) shift register, which must be connected to the clock CP and must trigger on the LOW to HIGH transitions. The data on the parallel inputs of this external shift register are loaded in parallel and shifted-out via input Isr into an internal shift register. The eleven serial input signals are in the order of shifting: A5, A4, A3, A2, A1, ton, Ion, It, rsv, rtl and ist. Signals A5, A4, A3, A2 and A1 represent the device talker and listener address. When signal It (either listener or talker) is HIGH, a listener addressing sets the talker to the idle state and a talker addressing sets the listener to the idle state (subset T5 and L3). With It LOW, the device can be addressed to be a listener and a talker. Because of the serial input procedure, all these input signals arrive in the interface functions of the IC between 16 and 32 clock cycles. The signals ton, Ion, rsv, rtl and ist are standard IEC/IEEE inputs. When using ton or Ion no controller action is possible. The output Oclr or Otrg is HIGH for one clock pulse if DCAS (device clear active state) or DTAS (device trigger active state) respectively is active. The output Oloc is HIGH when LOCS (local state) or LWLS (local with lock-out state) is active. Output OSRQ is HIGH when the rsv signal is read from the external shift register and the SRQS (request service state) is active. After this request has been answered by a serial poll, ORQS is HIGH in the APRS (affirmative poll response state). The inverted signal on ORQS must be multiplexed to bus-line DIO7, together with the status byte of the other DIO lines, when output Osp is HIGH in the SPAS (serial poll active state). When the device is in the SPAS state the signal rsv may be removed (can be checked on ORQS). N.B.: When the interface has asked for service via rsv and is addressed as talker in the serial poll mode, a handshake must be initialized by the device via Inba. Input Icats and output Otct are intended for use of this IC in a controller. When Icats is HIGH, the source handshake function will exit SIDS and SIWS and enter respectively SGNS and SWNS. When the controller function is not used, the input Icats must be connected to VSS. Output Otct is HIGH if the tct message is sent over the interface and the ACDS state is active. A HIGH on input Ipon sets each function to its initial state. This level can be set to LOW after the IC has received 32 clock pulses at stabilized supply voltage.
January 1995
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Philips Semiconductors
Product specification
IEC/IEEE bus interface
Note After power-on the input Ipon must stay LOW for at least 32 clock pulses, then HIGH for 32 clock pulses in order to force the function to its initial state. After this, Ipon must be set LOW. Input pins 1,2,3,36, 37, 38, 39 4 = IIDY 9 = Isr (note 1) 11 = IIFC 12 = Ipon 13 = IDAV 14 = Irdy 18 = IATN 24 = IRFD 25 = Inba 26 = IDAC 27 = lcats 28 = IREN 31 = CP Output pins 5 = OPP 8,7,6, = OP1 to OP3 10 = Ored 15 = ORFD 16 = ODAC 17 = Odvd 19 = OSRQ 21 = ORQS 22 = Odcd 23 = ODAV 29 = Osp 30 = Ota 32 = Oloc 33 = Oclr 34 = Otct 35 = Otrg Supply pins Fig.2 Pinning diagram; for abbreviations see the following list. 20 = VSS: 40 = VDD: Note HEF4738VP(N): 40-lead DIL; plastic (SOT129-1) = ID101 to 7:
HEF4738V LSI
input DIO input IDY not input shift register input IFC not input pon input DAV not input rdy not input ATN not input RFD input nba not input DAC inputs cats input REN not clock pulse input
output PP output P1 to P3 output red output RFD output DAC output dvd output SRQ not output RQS not output dcd output DAV not output sp output ta output loc output clr output tct output trg
more negative supply line more positive supply line
1. Isr is serial input for signals A5, A4, A3, A2, A1, ton, Ion, lt, rsv, rtl and ist.
( ): Package Designator North America
January 1995
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Philips Semiconductors
Note
IEC/IEEE bus interface
Because the circuit uses positive logic and the bus uses negative logic, all inputs and outputs to the bus must be inverted. For that reason, all terminals that are working with the bus have mnemonics which are the inverted ones of those on the bus.
Product specification
HEF4738V LSI
Fig.3 Block diagram.
Philips Semiconductors
Product specification
IEC/IEEE bus interface
LIST OF USED ABBREVIATIONS A1 to A5 ACDS APRS ATN AVD cats clr CVD DAC DAV DCAS dcd DCL DIO DTAS dvd EOI GTL IDY IFC ist LLO loc LOCS Ion It address acceptor data state affirmative poll response state attention address valid controller active or transfer state device clear command valid data accepted data valid device clear active state don't change data device clear data input output device trigger active state data valid device end of output/identify go to local identify interface clear individual status local lock-out local local state listen only decides whether the device can only be listener/talker or listener and talker simultaneously LWLS MLA MTA nba NRFD NDAC OTA P1 to P3 PCA pon PP PPC PPD January 1995 local with lock-out state my listen address my talk address new byte available not ready for data not data accepted other talk address parallel response messages parallel poll configure accepted power on parallel poll message enable parallel poll configure parallel poll disable 6 PPE PPU rdy red REN RFD RQS rsv rtl SDC SGNS SIDS SIWS sp SPAS SPD SPE sr SRQ SRQS SWNS ta tct ton trg UNL parallel poll enable
HEF4738V LSI
parallel poll unconfigure ready for next message ready for next shift cycle remote enable ready for data requested service request for service return to local selected device clear source generate state source idle state source idle wait state serial poll serial poll active state serial poll disable serial poll enable shift register service request request service state source wait for new cycle state talker active talk control talk only trigger unlisten
Philips Semiconductors
Product specification
IEC/IEEE bus interface
DC CHARACTERISTICS VSS = 0 V Tamb (C) VDD V Output current HIGH; see note Output current LOW; see note Quiscent device current Note 5 5 10 4,75 0,4 10 0,5 5 10 IDD VOL V VOH V 2,5 4,6 9,5 IOL -IOH SYMBOL -40 MIN. 3 1 3 2,7 9,5 50 100 MAX. + 25 MIN. 2,5 0,85 2,5 2,3 8,0 50 100 MAX.
HEF4738V LSI
+ 85 MIN. 2,0 0,65 2,0 1,8 6,3 375 750 MAX. mA mA mA mA mA A A
1. Output currents for pins: 5 = OPP, 6 = OP3, 7 = OP2, 8 = OP1, 15 = ORFD, 16 = ODAC; 19 = OSRQ, 23 = ODAV. These pins can drive one standard TTL load.
Fig.4 Waveforms showing data exchange in talker function.
Fig.5 Waveforms showing data exchange in listener function.
January 1995
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Philips Semiconductors
Product specification
IEC/IEEE bus interface
APPLICATION INFORMATION
HEF4738V LSI
Fig.6 Basic listener and talker. Serial and parallel poll are not implemented.
January 1995
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